The present disclosure relates to a wireless-interface module and an electronic apparatus that allow for easily performing internal processing such as debugging of a semiconductor device having a standardized interface.
In the past, while developing and designing the software and hardware of an electronic-circuit substrate including a plurality of large-scale integrated (LSI) circuits, a Joint-Test-Action-Group (JTAG) connector and/or other serial connectors were prepared for a designer to perform debugging of the software and get information about the internal state of the hardware. Namely, the above-described connector was connected to a personal computer (PC) for verification via a dedicated converter, so as to debug and/or verify the hardware and/or the software. The above-described technology is disclosed in Japanese Unexamined Patent Application Publication No. 8-114647, for example.
Each of FIGS. 14A and 14B is a block diagram showing the example where the LSI circuit is tested according to a known method.
First, FIG. 14A shows a substrate module 11 on which an LSI circuit to be tested (hereinafter referred to as a target LSI circuit) 10 is mounted. As shown in FIG. 14A, two types of connectors 12 and 13 connected to the target LSI circuit 10 are provided on the substrate module 11. The connector 12 supports a JTAG system and includes an Institute-of-Electrical-and-Electronics-Engineers (IEEE) 1149.1. The connector 13 is a general-purpose serial interface including a Recommended Standard 232 version C (RS-232C), a universal serial bus (USB), an IEEE 1394, and so forth.
FIG. 14B shows the example where a PC for debugging (host device) 20 performs debugging of the target LSI circuit 10. As shown in FIG. 14B, a connector 22 of the PC 20 is connected to a connector (the JTAG connector 12 in FIG. 14B) of the target LSI circuit 10 via a debugging cable 21. A predetermined signal is output from the connector 22 so that debugging is performed for the target-LSI-circuit-10 side.
Thus, wiring for debugging and connectors are required to perform the above-described processing. As the number of target LSI circuits increases, the wiring used for debugging becomes more complicated. Further, when serial debugging is performed, a predetermined number of connectors need to be added, as necessary, or it becomes necessary to switch among the wiring by using a switch integrated circuit (IC).
Recently, the capability of electrical products has been significantly increased. Further, the competition to decrease commodity prices has become fierce, and reduction of the commodity cycle has become significant.
On the other hand, when the product designing is actually performed, a substrate for design verification needs to be designed and/or mounted independently of a product substrate, where the substrate for design verification includes an interface (I/F) for debugging such as a Joint-Test-Action-Group (JTAG) device. Subsequently, the cost of product development is increased and the efficiency of product designing is decreased.
When the number of large-scale integrated (LSI) circuits mounted on the substrate increases, as is the case with the above-described configuration, the number of I/Fs for debugging is increased so that wiring provided for the I/Fs for debugging becomes complicated. Further, the design time and/or the mounting cost is increased, and verification processing is complicated.
Therefore, when debugging or the like is performed according to the above-described known method, it becomes difficult to efficiently adapt to the increased capability of electrical products, the fierce competition to decrease the commodity prices, and the commodity-cycle reduction or the like with regard to cost and/or speed.